Building a RISC-V CPU Core
About this courseSkip About this course
Building a RISC-V CPU Core is designed for anyone with a technical inclination who is interested in learning more about hardware. Whether you are new to digital logic or are a seasoned veteran, students will take away new skills that can be applied immediately. No prior knowledge of digital logic design is required.
LFD111x is a crash course in digital logic design and basic CPU microarchitecture. Using the Makerchip online integrated development environment (IDE), you will implement everything from logic gates to a simple, but complete, RISC-V CPU core. You will be amazed by what you can do using freely-available online tools for open source development. You will familiarize yourself with a number of emerging technologies supporting an open-source hardware ecosystem, including RISC-V, Transaction-Level Verilog, and the online Makerchip IDE.
This course is a hands-on experience with RISC-V and modern circuit design tools. You will walk away with fundamental skills for a career in logic design, and you will position yourself on the forefront by learning to use the emerging Transaction-Level Verilog language extension (even if you don’t already know Verilog).
At a glance
- Language: English
- Video Transcript: English
What you'll learnSkip What you'll learn
- Digital logic design (combinational and sequential logic)
- RISC-V (RV32I) instruction set architecture
- Basic CPU microarchitecture
- Transaction-Level Verilog basics
- Makerchip online IDE
- Chapter 1: Learning Platform
- Chapter 2: Digital Logic
- Chapter 3: The Role of RISC-V
- Chapter 4: RISC-V-Subset CPU
- Chapter 5: Completing Your RISC-V CPU
- Final Exam (Verified Certificate track only)