• Length:
    7 Weeks
  • Effort:
    1–2 hours per week
  • Price:

    FREE
    Add a Verified Certificate for $149 USD

  • Institution
  • Subject:
  • Level:
    Introductory
  • Language:
    English
  • Video Transcript:
    English
  • Course Type:
    Self-paced on your time

Prerequisites

The lab environment (Makerchip) is entirely online. The only system requirement is a web browser.

You may want to consider first taking Introduction to RISC-V (LFD110x) on edX, though this is not a prerequisite.

About this course

Skip About this course

Building a RISC-V CPU Core is designed for anyone with a technical inclination who is interested in learning more about hardware. Whether you are new to digital logic or are a seasoned veteran, students will take away new skills that can be applied immediately. No prior knowledge of digital logic design is required.

LFD111x is a crash course in digital logic design and basic CPU microarchitecture. Using the Makerchip online integrated development environment (IDE), you will implement everything from logic gates to a simple, but complete, RISC-V CPU core. You will be amazed by what you can do using freely-available online tools for open source development. You will familiarize yourself with a number of emerging technologies supporting an open-source hardware ecosystem, including RISC-V, Transaction-Level Verilog, and the online Makerchip IDE.

This course is a hands-on experience with RISC-V and modern circuit design tools. You will walk away with fundamental skills for a career in logic design, and you will position yourself on the forefront by learning to use the emerging Transaction-Level Verilog language extension (even if you don’t already know Verilog).

What you'll learn

Skip What you'll learn
  • Digital logic design (combinational and sequential logic)
  • RISC-V (RV32I) instruction set architecture
  • Basic CPU microarchitecture
  • Transaction-Level Verilog basics
  • Makerchip online IDE
  • Welcome!
  • Chapter 1: Learning Platform
  • Chapter 2: Digital Logic
  • Chapter 3: The Role of RISC-V
  • Chapter 4: RISC-V-Subset CPU
  • Chapter 5: Completing Your RISC-V CPU
  • Final Exam (Verified Certificate track only)

Meet your instructors

Steve Hoover
Founder
Redwood EDA

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