• Length:
    7 Weeks
  • Effort:
    1–2 hours per week
  • Price:

    Add a Verified Certificate for $149 USD

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  • Course Type:
    Self-paced on your time


  • A solid grounding in computer architecture will be helpful

About this course

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RISC-V is a free and open instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. This course will guide you through the various aspects of understanding the RISC-V community ecosystem, RISC-V International, the RISC-V specifications and how to help curate and develop them, and the technical aspects of working with RISC-V both as a developer and end-user.

"Introduction to Risc-V" is designed for RISC-V enthusiasts, hardware nerds, and anyone else interested in the details of how an open source ISA is breaking down barriers and opening up new opportunities in the microprocessor world.

This course contains a high level overview of RISC-V International, as well as how to get started working with the RISC-V ISA. The course gives you the foundational knowledge you need to effectively engage in the RISC-V community, contribute to the ISA specifications, or to develop the wide range of RISC-V software projects. After completing this course, you will have a better understanding of the terminology, resources, and workflow you will need to complete your RISC-V journey.

What you'll learn

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  • Describe the nature, history, and ongoing practices of RISC-V as a technology, an international organization, and a community of developers and implementers.

  • Explain how RISC-V technical working groups are organized.

  • Explain the basis of community-based open specification development, and how the RISC-V ISA is developed as an open specification.

  • Understand how people and organizations can benefit from and contribute to RISC-V.

  • Put the RISC-V ISA into action with a simulator booting the Linux operating system.

  • Welcome!

  • Chapter 1: Getting to Know RISC-V

  • Chapter 2: The RISC-V Story

  • Chapter 3: The RISC-V Community

  • Chapter 4: Developing RISC-V

  • Chapter 5: RISC-V in Practice

  • Final Exam (Verified track only)

Meet your instructors

Jeffrey "Jefro" Osier-Mixon
Program Manager
RISC-V International
Stephano Cetola
Technical Program Manager
RISC-V International

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